CH350 - Product Detail

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CH350

Circuit and Package

Circuit

Package

Features

Release to IECQ-CECC
Hermetically Sealed
High Density Packaging
1500V DC withstand Test Voltage
Low Input Requirements
High Current Transfer Ratio
RoHS Compliant

Description

The CH350 is a single channel device sealed in a small outline ceramic package suitable for mounting in hybrid sub-assemblies. It incorporates a high radiance LED and a high gain integrated photodetector. The output is an open collector Schottky clamped transistor.

Datasheet

Absolute Maximum Ratings (Ta=25°C)

Storage Temerature	-65°C to +150°C
Operating Temperature	-55°C to +125°C
Lead Soldering Temperature	260C for 10S, 1.6mm below seating plane where appropriate

Input Diode

Peak Forward Current	40mA	I_F (< 1mS duration)
Average Forward Current	20mA	I_F
Reverse Voltage	5V	V_R
Power Dissipation	35mW

Output Transistor

Supply Voltage	7V	V_CC (1 minute maximum)
Current	25mA	I_O
Collector Power Dissipation	40mW
Voltage	7V	V_O

Electro-optical Characteristics

T_{A =} -55°C to +125°C U.O.S.

All typical values at V_CC = 5V, T_A = 25°C (each channel where appropriate).

Parameter	Symbol	Test Conditions	Min	Type	Max	Units
High Level Output Current (See notes 1)	I_OH	I_F= 250µA, V_O= V_CC= 5.5V	-	20	250	µA
Lower Level Output Voltage (See note 1 & 9)	V_OL	I_F= 10mA, V_CC = 5.5V, I_OL(sinking) = 10mA,	-	0.4	0.6	V
High Level Supply Current	I_CCH	V_CC = 5.5V, I_F1 = I_F2 = 0	-	15	30	mA
Low Level Supply Current	I_CCL	V_CC = 5.5V, I_F1 = I_F2 = 13mA	-	15	36	mA
Input-Output Insulation Leakage Current (See notes 2 & 10)	I_I-O	RH = 45%, T_A = 25°C, t = 5S V_IO= 1500Vdc	-	-	1.0	µA
Input Forward Voltage (See note 1)	V_F	I_F= 10mA, T_A= 25°C	-	1.5	1.9	V
Input Forward Voltage (See note 1)	V_F	I_F = 20mA	-	-	1.9	V
Input Reverse Breakdown Voltage (See note 1)	B_VR	I_R = 10µA, T_A = 25°C	5	-	-	V
Propagation Delay Time to High Output Level (See note 1 & 5)	t_PLH	R_L = 510Ω, I_F= 13mA, T_A= 25°C, C_L = 15pF	-	-	200	nS
Propagation Delay Time to Low Output Level (See note 1 & 6)	t_PHL	R_L = 510Ω, I_F= 13mA, T_A= 25°C, C_L = 15pF	-	-	200	nS
Current Transfer Ratio	CTR	I_F= 10mA, V_O = 0.6V, V_CC= 5.5V	100	-	-	%

Typical Characteristics

T_A= 25°C

Parameter	Symbol	Test Conditions	Notes	Min	Type	Max	Units
Input Diode Temperature Coefficient	Δ_VF Δ_TA	I_F = 20mA	1	-	-1.9	-	mV/°C
Resistance	R_I-O	V₁₀= 500V	3	-	10¹²	-	Ω
Capacitance	C_I-O	f = 1MHz	3	-	1.9	-	pF
Input Capacitance	C_IN	f = 1MHz, V_F = 0	1	-	60	-	pF
Input-Input Leakage Current	I_I-I	45% Relative Humidity V_II = 500Vdc, t = 5S	4	-	0.5	-	nA
Resistance	R_I-I	V_II= 500Vdc	4	-	10¹²	-	Ω
Capacitance	C_I-I	f = 1MHz	4	-	0.6	-	pF
Output Rise (10-90%)	tr	R_L = 510Ω, C_L = 15pF, I_F = 13mA	1	-	35	-	nS
Output Fall Time (90-10%)	tf	R_L = 510Ω, C_L = 15pF, I_F= 13mA	1	-	35	-	nS
Common Mode Transient Immunity at Logic High Output Level	CM_H	V_O (min) = 2V, V_CM = 10V (peak) R_L = 510Ω, I_F = 0mA	1 & 7	-	1000	-	V/µS
Common Mode Transient Immunity at Logic Low Output Level	CM_L	V_O (max) = 0.8V, V_CM = 10V (peak) R_L = 510Ω, I_F = 10mA	1 & 8	-	1000	-	V/µS

Notes: (Apply typically to 16 pin package)

1. Each channel, where appropriate.

2. Measured between pins 1 through 4 shorted together, and pins 9 through 16 shorted together.

3. Measured between pins 1 and 2, or 5 and 6 shorted together, and pins 9 through 16 shorted together.

4. Measured between pins 1 and 2 shorted together, and pins 5 and 6 shorted together.

5. The t_PLH propagation delay is measured from the 6.5mA point on the trailing edge of the input pulse to the 1.5V point on the trailing edge of the output pulse.

6. The t_PHL propagation delay is measured from the 6.5mA point on the leading edge of the input pulse to the 1.5V point on the leading edge of the output pulse.

7. CM_H is the maximum tolerable common mode transient to assure that the output will remain in a high logic state (i.e., V_O > 2.0V).

8. CM_L is the maximum tolerable common mode transient to assure that the output will remain in the logic low state (i.e., V_O < 2.0V).

9. It is essential that a bypass capacitor (0.1 to 0.1µF, ceramic) be connected from pin 10 to pin 15. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20mm.

10. This is a momentary withstand test, not an operating condition.

Reliability and Approvals

IECQ-CECC_Certification

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